1. Field of the Invention
The present invention relates to a semiconductor device for outputting a signal with a given accurate phase held relative to an externally-input signal, a semiconductor system composed of such semiconductor devices, and a digital delay circuit employed in the semiconductor system. More particularly, this invention is concerned with a synchronous semiconductor memory from which a signal is output with a given phase held relative to an external clock despite a change in ambient temperature or a fluctuation in supply voltage.
2. Description of the Related Art
Normally, a semiconductor integrated circuit (including a large scale integration (LSI)) accepts an external signal, and outputs an output signal after carrying out processing according to the input signal. Timing relative to an external input signal according to which an output signal is provided is therefore important. In a general-purpose LSI, the timing is usually determined as one of the specifications for the LSI. Taking a dynamic random access memory (DRAM) for instance, a maximum frequency of an address signal as well as the timing of outputting data relative to a transition edge of the address signal and a data setup time required for writing data are stipulated.
In recent years, it has been earnestly requested to increase the operating speed of an interface in line with an increase in frequency of a clock used in a CPU within a computer system or with increases in processing speeds of other various electronic circuits. For example, a CPU using a clock with a frequency of 100 MHz or higher has made its debut. However, the access rate and data transfer rate of a Dram widely adopted as a main memory are lower than the frequency of the clock by one decade. Various novel DRAM architectures such as a synchronous DRAM (SDRAM) permitting a data transfer rate of 100 MHz or higher have been proposed to date.
The SDRAM inputs or outputs data synchronously with a high-frequency clock that is input externally, and includes a plurality of units capable of inputting or outputting a plurality of bits of data in parallel. A method of interfacing an external unit at a high speed falls into a method of converting a plurality of bits of data into serial data and a method of pipelining internal operations and carrying out the operations of pipes in parallel. The description will proceed by taking a DRAM having a pipelined architecture as an example. However, the present invention is not limited to this kind of DRAM.
In the SDRAM, internal operations and input or output of signals are carried out synchronously with a clock supplied externally. When this SDRAM is employed in a high-speed memory system, if the SDRAM is accessed continuously, a clock access time tAC that is a time interval between the leading edge of a clock and the output of data, and an output data retention time tOH that is a time interval starting with the leading edge of the clock, during which data is retained, are significant. The times tAC and tOH are determined in relation with the same path. When consideration is taken into a difference in characteristic of one SDRAM from another, and the temperature dependency and supply voltage-dependency of the SDRAM, the times tAC and tOH do not coincide with each other but differ from each other to some extent. The time comparable to the difference is the time during which data is uncertain, the time during which it is uncertain what kind of data is output, the time is unusable by a memory system, or is a so-called dead band. It is important to make the uncertain data time as short as possible.
To shorten the uncertain data time, it should be guaranteed that despite a difference in characteristic, a change in temperature, or a fluctuation in supply voltage, data is always output with a given phase held relative to an external clock, or in other words, the clock access time tAC is constant all the time. For example, if it is preferable that output of data is carried out synchronously with the rise of an external clock CLK, the clock access time tAC should be zero all the time.
The necessity of providing an output signal synchronously with an externally-input signal has been described by taking a synchronous DRAM as an example. This is not limited to the synchronous DRAM but is true among many semiconductor devices. As far as the interior of a semiconductor device is concerned, various measures can be taken to enable the semiconductor device to carry out desired operations. For outputting the result of processing performed internally by a semiconductor device, the relationships of the semiconductor device with other semiconductor devices must be defined. It is important to stabilize the timing of the output. The present invention relates to an art for stabilizing the timing of output relative to an external clock in a semiconductor device.
An object of the present invention is to realize a semiconductor device capable of outputting data with a given phase held relative to an external clock CLK despite a difference in characteristic, a change in temperature, or a fluctuation in supply voltage.
A semiconductor device in accordance with the present invention comprises an input circuit for inputting an external input signal and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing of an output signal sent from the output circuit so that the output signal exhibits a given phase relative to the external input signal. The output timing control circuit includes a delay circuit for which a magnitude of a delay can be specified, and which delays a reference signal by the specified magnitude, and applies the resultant reference signal as an output timing signal to the output circuit, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of the comparison performed by the phase comparison circuit.
In the semiconductor device of the present invention, the magnitude of a delay needed for adjusting timing by the output timing control circuit is not fixed. For adjusting the magnitude of a delay so that a signal output from an actual circuit has a given phase relationship relative to an external clock (corresponding to the reference signal) output from the input circuit, the phase relationship of the output signal relative to the external clock can be retained accurately at a given value despite a difference in characteristic of one semiconductor device from another, a change in temperature, or a fluctuation in supply voltage.
What is compared with the external clock must be a signal delayed by the same magnitude as the magnitude of a delay produced by the actual circuit. From this viewpoint, a dummy input circuit for producing the same magnitude of a delay as the input circuit and a dummy output circuit for producing the same delay as the output circuit are included. For comparing phases, it is essential that an output signal of the output circuit makes a state transition. During normal operation, the output circuit provides output data. The output data is a varying signal that may be at a high level or at low level. For comparing the phase of an output signal of the output circuit with the phase of the external clock during a normal operation, the phase comparison circuit 22 judges whether or not the output signal has made a state transition. Only when the output signal has made a state transition, are phases compared. If the output signal makes no state transition, the delay control circuit gives control so that the ongoing magnitude of a delay can be retained. Thus, if the output signal makes no state transition, the output signal is fed back so that control is given until the output signal is in phase with the external clock.
In another configuration, initialization is carried out before a normal operation starts. During the initialization, dummy data that makes a state transition at intervals of a given cycle is output. The phase of the dummy data is compared with that of the external clock. The dummy data is fed back so that control is given until the dummy data is in phase with the external clock. After the dummy data is in phase with the external clock, an adjusted magnitude of a delay is retained. The dummy data makes a state transition at intervals of a given cycle without fail. The phase comparison circuit can compare phases merely by judging in which direction the dummy data makes a state transition.
Using the dummy output circuit, a signal suitable for judging a phase which is independent of an output signal of the output circuit can be output all the time. This means that dummy data can always be output for feedback control. Moreover, if the dummy data is a signal that makes a state transition by taking time longer than the cycle of the clock, the power consumption of the circuit can be minimized.
Furthermore, a second output timing control circuit to be associated with the dummy output circuit is included separately from the first output timing control circuit associated with the output circuit. During initialization, an output signal and dummy output signal are synchronized with the external clock. This means that the output signal and the dummy output signal become synchronous with each other. Thereafter, the dummy output signal is fed back to the first output timing control circuit for the purpose of giving control. Owing to this configuration, the dummy output circuit can be used to achieve adjustment even under the effect of a load connected to the actual output circuit.